In the field of a high voltage withstanding semiconductor device that controls a voltage exceeding several hundred volts, element characteristics wherein heat emission, that is to say, loss is suppressed are required because the current handled is great. In addition, as for a driving system of a gate that controls this voltage and current, a voltage drive element of which the driving circuit is small so that the loss therein is small is desirable.
In recent years, because of the above described reasons, an insulated gate bipolar transistor, that is to say, an IGBT, has come into wide use as an element wherein a voltage drive is possible and loss is small in this field. The structure of this IGBT is a structure wherein the impurity concentration of the drain is lowered so as to secure the withstanding voltage in a MOS (metal oxide semiconductor) transistor and the drain can be regarded as a diode in order to reduce the drain resistance.
Thus, a diode carries out a bipolar operation in an IGBT and, therefore, in the present application the source of the MOS transistor of an IGBT is referred to as an emitter and the drain is referred to as a collector.
A voltage of several hundred volts is applied between the collector and the emitter of an IGBT, which is a voltage drive element and which is controlled by the gate voltage of which the voltage is ± several volts to several tens of volts. In addition, in many cases an IGBT is used as an inverter, wherein the voltage between the collector and the emitter is low in the case that the gate is in the on condition so that a great amount of current flows while no current flows and the voltage between collector and the emitter is high in the case that the gate is in the off condition.
Since the operation of an IGBT is carried out conventionally in the above described mode, the loss is divided into constant loss, which is a product of current and voltage in the on condition, and switching loss at the time of transition wherein the on condition and the off condition are switched. The product of leak current and voltage in the off condition is so small that it can be ignored.
On the other hand, it is important to prevent breakdown of the element during an abnormal state such as, for example, in the case that the load is short circuited. In this case, the gate is turned on while the power source voltage of several hundred volts is applied between the collector and the emitter so that a large current flows.
In an IGBT having a structure wherein a MOS transistor and a diode are connected in series the maximum current is controlled by the saturation current of the MOS transistor. Therefore, the current control works even at the time of short circuiting, as described above, so that breakdown of the element due to heat emission of a constant period of time can be prevented.
In IGBTs of recent years, however, a trench gate IGBT that has adopted a trench gate in order to further reduce loss has come into wide use. Since a trench gate IGBT is an element wherein the MOS transistor portion is miniaturized, the gate capacitance becomes large and the saturation current becomes very large at the time of short circuiting so as to tend to break down for a short period of time due to a great heat emission.
Furthermore, in recent years there has been a phenomenon wherein a malfunction is caused by the occurrence of oscillation in the gate voltage, gate current, collector-emitter voltage and collector current at the time of short circuiting due to the feedback capacitance of an IGBT as described in, for example, “Proceedings of 1998 International Symposium on Power Semiconductor Devices & ICs, p. 89.” Such an oscillation phenomenon due to the feedback capacitance has become an increasingly serious problem in an element of which the gate capacitance is large such as a trench gate IGBT. A prior art and problems thereof are described from such a point of view in the following.
FIG. 52 is a cross sectional view schematically showing the configuration of a high voltage withstanding semiconductor device according to a prior art. In reference to FIG. 52, a p-type body region 102 is formed in the first main surface of an n− silicon substrate 101, which has a concentration of approximately 1×1014 cm−3. The concentration of this p-type body region 102 is approximately 1×1016 cm−3 to 1×1018 cm−3 and the depth from the first main surface is approximately 3 μm. An n-type emitter region 103 and a p+ impurity region 106 are formed in the first main surface within this p-type body region 102.
The concentration of this n-type emitter region 103 is 1×1019 cm−3, or greater, and the depth is approximately 0.5 μm. The p+ impurity region 106 is formed so as to provide a low resistance contact with p-type body region 102 and has the concentration of approximately 1×1020 cm−3.
A trench 101a for a gate, of which the depth is 3 μm to 10 μm, is created so as to penetrate this n-type emitter region 103 and p-type body region 102 and to reach n− silicon substrate 101. The pitch of this trench 101a for a gate is, in general, 2.0 μm to 6.0 μm. A gate insulating film 104a, made of, for example, a silicon oxide film having a thickness of 30 nm to 200 nm, is formed so as to line the inner surface of this trench 101a. A gate electrode 105a made of polycrystal silicon, into which phosphorous, for example, is introduced at a high concentration, is formed so as to fill in this trench 101a for a gate.
An insulating film 109 is formed on the first main surface and a hole 109a for opening a portion of the first main surface is provided in this insulating film 109. A barrier metal layer 110 is formed at the bottom of this hole 109a. An emitter electrode 111 is electrically connected to p-type body region 102 and to n-type emitter region 103 via this barrier metal layer 110.
An n-type buffer region 107 and a p-type collector region 108 are formed in the second main surface of n− silicon substrate 101. A collector electrode 112 made of, for example, an aluminum compound is electrically connected to this p-type collector region 108.
In the above described semiconductor device, for example, at the time of the connection of an inverter, the gate potential G of gate electrode 105a is −15V in the off condition in reference to the emitter potential E and is a control signal in a pulse form set at +15V in the on condition while the collector potential of collector electrode 112 follows the gate potential so as to be approximately in the operational voltage range between the power supply voltage and saturation voltage.
FIG. 53 shows a schematic cross sectional view showing a terminal portion of the cell region of a high voltage withstanding semiconductor device according to a prior art. In reference to FIG. 53, a p-type impurity region 121 is formed so as to have a concentration of, for example, 1×1016 cm−3 to 1×1018 cm−3 in the first main surface of the terminal portion of the region wherein a plurality of cells are arranged. This p-type impurity region 121 is formed deeper than p-type body region 102 from the first main surface and has a structure that mitigates the electrical field due to the potential gap between the outer most peripheral portion of the chip and the cell region.
The structure of FIG. 52 has been improved so as to gain semiconductor devices as disclosed in U.S. Pat. No. 6,040,599 and in Japanese Patent Laying-Open No. 9-331063. In the following, these semiconductor devices are described.
FIG. 54 is a cross sectional view schematically showing the configuration of the semiconductor device disclosed in U.S. Pat. No. 6,040,599. In reference to FIG. 54, the structure of this semiconductor device substantially differs from the configuration of FIG. 52 in the point that a high concentration n-type impurity region 114 is added. This high concentration n-type impurity region 114 is provided in a portion that contacts p-type body region 102 within n− silicon substrate 101.
Here, the parts of the configuration other than this are substantially the same as the above described configuration shown in FIG. 52 and, therefore, the same signs are attached to the same members, of which the descriptions are omitted.
In the configuration shown in FIG. 54, a barrier against carriers can be formed because of the existence of high concentration n-type impurity region 114. Therefore, the carrier concentration on the emitter side of n− silicon substrate 101 can be increased without reducing the area of p-type body region 102. Thereby, the on resistance and the on voltage can be reduced.
FIG. 55 is a cross sectional view schematically showing the configuration of a semiconductor device disclosed in the Japanese Patent Laying-Open No.9-331063. In reference to FIG. 55, the configuration of this semiconductor device differs from the configuration shown in FIG. 52 in the point that a so-called emitter trench is provided. This emitter trench is formed of a trench 101b for an emitter provided in the first main surface of the substrate, an insulating film 104b for an emitter formed along the inner surface of this trench 101b for an emitter and an emitter electrode 105b that fills in trench 101b for an emitter. This electrode 105b for an emitter is electrically connected to an emitter electrode 111 via a hole 109b provided in insulating layers 109A and 109B. Such an emitter trench is provided in a region that is, for example, sandwiched by two trenches 101a for gates.
Here, the parts of the configuration other than this are substantially the same as the above described configuration shown in FIG. 52 and, therefore, the same signs are attached to the same members, of which the descriptions are omitted.
According to the above described gazette, when the distance dx between trench 101a for a gate and trench 101b for an emitter is 0.2 μm and the pitch Pi of trenches 101a for gates is 5.3 μm in the configuration of FIG. 55, the carrier concentration on the emitter side increases and the on resistance (that is to say, voltage between the collector and the emitter in the IGBT under a constant current; saturation voltage) of the IGBT can be reduced so that the steady-state loss can be suppressed.
However, in the configuration (FIG. 54) disclosed in U.S. Pat. No. 6,040,599 the depletion layer becomes resistant to expansion from gate 105a because of the existence of high concentration n-type impurity region 114. Thereby, the gate capacitance on the drain side becomes great so that a problem arises wherein oscillation occurs at the time of short circuiting.
In addition, in the configuration disclosed in U.S. Pat. No. 6,040,599 the saturation current becomes very great in the case that trenches 101a for gates are designed with a conventional pitch and a problem arises wherein the withstanding capacity, itself, against short circuiting is lowered.
Furthermore, in the configuration disclosed in U.S. Pat. No. 6,040,599, since the gate capacitance is great, a problem arises wherein a switching time delay occurs and a gate drive circuit of a large capacitance becomes necessary.
In addition, in the configuration (FIG. 55) disclosed in Japanese Patent Laying-Open No. 9-331063, the saturation voltage is lowered by reducing (2×dx)/Pi. In order to lower the saturation voltage, however, it is not necessary for conductive layer 105b, which fills in trench 101b for an emitter, to be at the emitter potential and oscillation control is not taken into consideration. Therefore, in the case that the potential of conductive layer 105b, which fills in trench 101b for an emitter, becomes of the gate potential or of a floating potential or in the case that other conditions have fluctuated, a problem arises wherein oscillation occurs at the time of short circuiting even if conductive layer 105b becomes of the emitter potential. This is described in detail in the following.
In order to gain the effects of the invention disclosed in Japanese Patent Laying-Open No. 9-331063, it is essential for (2×dx)/Pi to be small. Here, (2×dx)/Pi is a ratio of p-type body region 102 that is connected to the emitter potential E in a cell.
In addition, in Japanese Patent Laying-Open No. 7-50405 that discloses an invention that is similar to the invention according to Japanese Patent Laying-Open No. 9-331063, it is cited as a requirement that (Pi+dy)/(2×dx) is no less than five when the difference between the depth of a trench and the depth of a p-type body region is dy. Here, dx is the width of a p-type body region that is connected to the emitter potential E and that corresponds to one channel of a MOS transistor.
That is to say, in the invention according to Japanese Patent Laying-Open No.9-331063, the requirement for the lowering of the saturation voltage specifies that Pi/dx is large, irregardless of dy and does not specify that conductive layer 105b, which fills in trench 101b for an emitter, becomes of the emitter potential.
FIG. 56 is a diagram showing an equivalent circuit of an IGBT. In reference to FIG. 56, in the inventions according to Japanese Patent Laying-Open No.7-50405 and Japanese Patent Laying-Open No.9-331063, Pi/dx is increased so that Pi is increased in reference to dx, which is restricted because of a microscopic processing limitation. Therefore, a portion of a MOS transistor structure formed in a unit area is reduced. Accordingly, the voltage drop Vmos in the MOS transistor Tr portion becomes greater than that in the structure of FIG. 52 wherein there is no emitter trench.
On the other hand, in the inventions according to Japanese Patent Laying-Open No.7-50405 and Japanese Patent Laying-Open No.9-331063, the carrier concentration in a region in the vicinity of the emitter side of n-type substrate 101 rises, as shown in Japanese Patent Laying-Open No. 7-50405 and, therefore, the voltage drop Vdi in the diode Di portion becomes smaller than in the structure of FIG. 52 wherein there is not emitter trench.
The saturation voltage of the IGBT is represented by the sum of Vmos and Vdi and, therefore, the condition wherein (Pi+dy)/(2×dx) is no less than five, as described in Japanese Patent Laying-Open No. 7-50405, has no basis.
In reference to this, “Proceedings of 1995 International Symposium on Semiconductor Devices & ICs,” pp. 486-491 describes wherein in the case that a parameter of the MOS transistor portion is made a constant, the saturation voltage rises because the voltage drop in the MOS transistor becomes great when Pi/dx is made too large.
The optimal range of Pi/dx changes depending on the parameters of the MOS transistor portion, such as the thickness of the gate insulating film and the channel length, the parameters of the diode portion, such as the thickness of the substrate and the lifetime within the substrate, the depth of the trench, current density, and the like, when the collector injection efficiency is set at a constant, as shown in “Proceedings of 1998 International Symposium on Semiconductor Devices & ICs,” pp. 43-46.
However, when the existing general parameters of an IGBT are used and dx is set at 1.5 μm to 2.5 μm, which are realistic values, the optimal Pi/dx becomes approximately five to eight in a high voltage withstanding IGBT of the 5000 V class. In addition, in the case that the collector injection efficiency is low, such as in an NPT (non-punch through) type IGBT of the 1000 V class, the effects of lowering the saturation voltage can be gained when Pi/dx is approximately eight while, contrarily, the saturation voltage increases when Pi/dx is approximately three in the case that dx is 2 μm and the current density is 100 A/cm2.
Thus, in the invention according to Japanese Patent Laying-Open No. 9-331063, the necessity for the conductive layer 105b, which fills in trench 101b for an emitter, to be of the emitter potential merely requires that no channel be formed on a sidewall of trench 101b for an emitter. However, in the configuration shown in FIG. 55 disclosed in the above described gazette, an n+ emitter region 103 is not provided on a sidewall of trench 101b for an emitter so that no channel is formed on the sidewall. Accordingly, conductive layer 105b, which fills in trench 101b for an emitter, is not at the emitter potential and, even in the case that it is, for example, at a floating potential or at the gate potential, the effects of the reduction of the saturation voltage can be gained so that the necessity for lowering the saturation voltage does not require conductive layer 105b, which fills in trench 101b for an emitter, to be at the emitter potential.
Accordingly, in the case that the potential of conductive layer 105b, which fills in trench 101b for an emitter, becomes of the gate potential or at a floating potential, or in the case that other conditions fluctuate even if the potential of the conductive layer becomes of the emitter potential, oscillation occurs at the time of short circuiting.
Here, the oscillation of an IGBT is briefly described.
FIG. 57 is a diagram showing an equivalent circuit of an IGBT. In reference to FIG. 57, in the case that the gate of a MOS transistor Tr is turned on under the short circuited condition and the gate voltage becomes Vg, MOS transistor Tr changes from the off condition to the on condition and, therefore, the potential Vd on the drain side suddenly drops so as to have a change of dVd. On the other hand, since the main current i changes by di/dt, the potential Vs on the source side rises by Re·di/dt when the resistance of the emitter is Re.
Accordingly, when the capacitance on the drain side is Cd and the capacitance on the source side is Cs, the current igd that flows into the gate from the drain side becomes as follows:igd=Cd·dVd/dt (dVd/dt<0)
In addition, the current igs that flows into the gate from the source side becomes as follows:igs=Cs·Re·di/dt (di/dt>0)
Accordingly, the sum of the current ig that flows into the gate becomes igd+igs and the gate voltage changes by dVg=Rg·ig so as to become Vg′ when the gate resistance is Rg. Here, Vg′ is represented as follows:Vg′=Vg+Rg·ig=Vg+Rg·(Cd·dVd/dt+Cs·Re·di/dt)
Since, in practice, a time difference occurs between dVd/dt and di/dt due to parasitic inductance, a phenomenon, which is ignored here because a qualitative description is given, occurs wherein gate voltage surges at the on time.
In addition, Cd and Cs change due to Vd and Vg and this change is also ignored in the qualitative portion of the present description.
In addition, because of the above reason, when the main current is in the short circuited condition so that the MOS transistor is in the saturation condition, the current change di=i′−i becomes as follows:di=gm (Vg′−Vth)k−gm (Vg−Vth)k
Here, k has a value of from 1 to 2. gm is a transconductance.
In addition, the potential Vd′ on the drain side again changes depending on the change in this current. The behavior of the IGBT at the time of short circuiting changes depending on how the above repeated feedback is applied.
At the time of the change from the off condition to the short circuiting (on condition), in the case of Cs·Re·di/dt+Cd·dVd/dt>0, Vg′ becomes as follows when Vg′ is the gate voltage dt periods of time after Vg:Vg′=Vg+Rg·ig=Vg+Rg·(Cd·dVd/dt+Cs·Re·di/dt)
Because of (Cd·dVd/dt+Cs·Re·di/dt)>0 in the above equation, Vg′>Vg is gained.
That is to say, the gate voltage increases further. The main current i′ after dt periods of time is represented as follows;i′=gm(Vg′−Vth)k
Therefore, together with the increase in the gate voltage, the main current increases further. Positive feedback is thus applied.
In addition, together with the increase in the gate voltage, the voltage Vd between the drain and the source drops further and the change therein, dVd′, is smaller than dVd. Thus, dVd/dt becomes smaller over time and, therefore, the change in Vg becomes smaller over time. Furthermore, di/dt becomes smaller over time and, therefore, convergence is finally gained such that no oscillation occurs.
When Cs·Re·di/dt+Cd·dVd/dt is very large, however, the positive feedback is too great so that the main current momentarily becomes very great and a breakdown may occur due to heat emission.
In the case of Cs·Re·di/dt+Cd·dVd/dt<0, negative feedback is applied.
That is to say, the effects of the lowering of the potential Vd, in the vicinity of the drain, due to the turning on of the gate is great so that a current flows into the gate.Vg′=Vg+Rg·ig=Vg+Rg·(Cd·dVd/dt+Cs·Re·di/dt)
Because of (Cd·dVd/dt+Cs·Re·di/dt)<0 in the above equation, Vg′<Vg is gained.
That is to say, the gate voltage after dt periods of time is lowered.
Because i′=gm (Vg′−Vth)k, the main current, in turn, decreases together with the lowering of the gate voltage. Under this condition, the main current i′ becomes lower.
In the case of Vg′<Vth, the channel that has once been turned on converts to the off condition and, therefore, i′ decreases remarkably while Vd′ increases remarkably. Then, in this case there is, in turn, an opposing change from the on condition to the off condition so as to be dVd′/dt>0 and di′/dt<0 and, therefore, the MOS transistor portion of the IGBT converts to the condition that is close to off condition wherein Cs·Re·di′/dt+Cd·dVd′/dt>0 and, in turn, the following is again gained.Vg″=Vg′+Rg·ig′=Vg′+Rg·(Cd·dVd′/dt+Cs·Re·di′/dt)
Then, because of Re·di′/dt+Cd·dVd′/dt>0, Vg″>Vg′ is gained so that the gate potential becomes very high.
Though this is repeated so as to cause an oscillation, in the case that the relationship between dVd (n) that has occurred at the nth oscillation and dVd (n+1) that has occurred at the (n+1)th oscillation is dVd (n)>dVd (n+1), the oscillation converges. Though in the case of dVd (n)<dVd (n+1), the oscillation becomes greater, dVd becomes of the maximum from the condition sufficiently turned on to the condition sufficiently turned off and, therefore, the oscillation amplitude has an upper limit and the oscillation continues under that condition.
Here, the coefficient cited as a feedback coefficient in the present application is a ratio of the change in dVd, dVd (OFF→ON)/dVd(ON→OFF), being a ratio of dVd in the case of conversion from the off condition to the on condition to dVd in the case of subsequent conversion from the on condition to the off condition wherein no less than −1 (finally converging to −1), approximately −0.9 (oscillation gradually converges) and approximately −0.1 (oscillation converges suddenly) are cited as examples.
Here, dVd (OFF→ON)/dVd(ON→OFF) and dVd (ON→OFF)/dVd(OFF→ON) are assumed to be the same (in practice).
In addition, in the configuration (FIG. 55) of Japanese Patent Laying-Open No. 9-331063, an emitter trench of a considerable width, relative to the pitch Pi of trench 10a for a gate, is required or a p-type body region 102 at a floating potential requires a considerable amount of space relative to the pitch Pi of trench 101a for a gate.
In the case that an emitter trench of a broad width is created, the conductor filled therein is deposited very thickly so that it is necessary to be etched back and a problem arises wherein productivity is lowered.
In addition, though in the case that dx is made very small the problem of productivity is resolved, the density of the MOS transistor becomes great and, therefore, a problem arises wherein a delay in switching time occurs due to the increase in gate capacitance and a gate drive circuit of a large capacitance is required.
In addition, because of the increase in the MOS transistor density, the lowering of the withstanding capacity against short circuiting due to the increase in the saturation current also becomes a problem.
In addition, in a technique wherein a p-type body region of a wide floating potential is secured, there is a possibility that latch up may occur due to a lack of area of the p-type body region of the emitter potential as shown in, for example, U.S. Pat. No. 4,994,871.